A semiconductor integrated circuit chip is typically fabricated with a back-end-of-line (BEOL) interconnect structure, which comprises multiple levels of metal lines and inter-level metal vias, to connect various integrated circuit components and devices that are fabricated as part of a front-end-of-line (FEOL) layer of the semiconductor integrated circuit chip. Current state of the art BEOL process technologies typically implement copper to form BEOL interconnects, as the use of copper material is known to significantly reduce resistance in the BEOL interconnect structure, resulting in improved conduction and higher performance. As copper interconnect structures are scaled down, however, there is a significant increase in the resistivity and current density within the copper interconnect structures, which is undesirable. The increase in current density in copper interconnect structures causes an increase in the current-driven electromigration of copper atoms. In the context of copper interconnect structures, electromigration is the transport of copper atoms caused by the gradual movement of ions in the copper material due to momentum transfer between conducting electrons and diffusing copper atoms. The electromigration of copper atoms can lead to various defects in copper interconnect structures such as voids and hillock defects.
Conventional metallic interconnect structures utilize copper diffusion barrier layers (e.g., tantalum nitride (TaN)) to line exposed sidewall and bottom surfaces of openings (e.g., trench openings and via openings) that are patterned in an interlevel-dielectric (ILD) prior to filling the openings with copper material. The diffusion barrier layer prevents copper from diffusing into the dielectric material of the ILD layer and damaging the BEOL structure. As copper interconnects are scaled down, however, the use of diffusion barrier layers becomes problematic.
For example, copper diffusion barrier layers must be made sufficiently thick to adequately prevent diffusion of copper atoms into the ILD layer. The required thickness of the copper diffusion barrier layer remains relatively constant as the line width of copper interconnects scales down. As such, the amount (volume) of the metal line which is composed of copper is reduced which, in turn, affects various line width-dependent characteristics such as grain structure and resistivity.
Moreover, since diffusion barrier layers are typically formed of a material (e.g., TaN) which does not sufficiently act as a wetting layer for electroplated copper, a thin seed layer is typically formed via PVD or CVD on the diffusion barrier layer prior to the copper fill. The combined thickness of the diffusion barrier layer and the seed layer can adversely affect the copper filling ability due to a further narrowing of already narrow lines. The combination of poor wetting, vertical sidewalls, and narrow trenches can result in a discontinuous seed layer coverage. Such poor seed layer coverage can lead to voids and other defects in the copper line, which in turn can weaken the adhesion between the copper interconnect and the diffusion barrier layer. Both voids and poor adhesion contribute to copper electromigration defects.
For advanced BEOL technologies, fabrication methods which replace conventional copper diffusion barrier layers with lower resistivity materials such as cobalt and ruthenium are being considered. However, the use of cobalt and ruthenium barrier/liner layers for copper interconnects can be problematic in that such materials do not provide as strong a level of adhesion to the dielectric material of the ILD layer as does conventional TaN or TiN barrier layers and, thus, the interface adhesion between a cobalt or ruthenium liner layer and the dielectric material of the ILD layer is weak. This weaker interface can lead to the formation of voids between the copper material and the ILD due to peel-off of exposed upper portions of the liner/ILD interface during a chemical-mechanical polish (CMP) process as a result of the shear mechanical forces applied to the liner/ILD interface.